Honored ContributorIt seems that Modelsim doesn't support VHDL Configuration feature.
One of my module contain two architectures, in the top level VHDL file use VHDL configuration to use the two different architectures. During modelsum pre-simulation, it seems to always use the last architecture. Anything mistake? Thanks for any response.
Honored ContributorDid you specify the configuration as your simulation target? If you specify the entity, it will simulate without the effect of the configuration.
Honored ContributorHonored ContributorConfigurations aren't automatically applied to entities in Modelsim. If you are simulating a test bench, you need to instantiate the configuration rather than the entity. If you are instantiating a component, you can bind it to the configuration with a configuration specification in the architecture declarative region:
for inst: my_comp
use configuration work.cfg;
vsim work.cfgvsim work.entityI am using Entity-Architecture Pair Configuration instead of Lower-Level Configuration, so that I can decribe two architectures for the same entity in a single VHDL file, and then use Entity-Architecture Pair Configuration to configurate the entity in the upper-level VHDL file.
Do you know with Entity-Architecture Pair Configuration, how to make modelsim understand the configuration?configuration con of FREQMeasure_SingleChannel is
for rtl
for U1: FREQMeasure_PeriodCounterDuringStrobe USE ENTITY WORK.FREQMeasure_PeriodCounterDuringStrobe(WithStrobeOutput);
end for;
for U2: FREQMeasure_PeriodCounterDuringStrobe USE ENTITY WORK.FREQMeasure_PeriodCounterDuringStrobe(WithoutStrobeOutput);
end for;
end for;
end con; It depends on what you are simulating. Do you have a test bench that instantiates the entity? If so, then you need to change it to instantiate the configuration, e.g.
dut: configuration work.con generic map (...) port map (...);I instantiate lots of components using generate clause, pls see below:
U2: FOR i IN 0 TO (GEN_TOTAL_CHANNEL - 1) GENERATE
channel_x: FREQMeasure_SingleChannel GENERIC MAP(GEN_BENCHMARK_FREQUENCE, GEN_MAX_TARGET_FREQUENCE, GEN_MIN_TARGET_FREQUENCE, GEN_T_STROBE_WIDTH)
PORT MAP (csi_freqmeasure_benchmark_clock_export, cos_freqmeasure_channel_in_export(i), s_strobe, csi_freqmeasure_clock_reset_n, s_A_TargetCounter(i), s_A_BenchCounter(i));
END GENERATE;I have tried:
for channel_x: FREQMeasure_SingleChannel
use configuration work.con;for U2: FREQMeasure_SingleChannel
use configuration work.con;You need to put the configuration specification in the declarative region for the generate block, e.g.
U2: FOR i IN 0 TO (GEN_TOTAL_CHANNEL - 1) GENERATE
FOR channel_x : FREQMeasure_SingleChannel
use configuration work.con;
BEGIN
-- Your instance here
end generate;
It works...
Thanks a lot!Honored ContributorAnother problem occurs :(
use configuration work.con can make modelsim select the correct configuration, but when I return back to SOPC Builder and try to re-generate system, the following error reported: Error: freqmeasure_wholesystem_inst: Error (10481): VHDL Use Clause error at FREQMeasure_WholeSystem.vhd(149): design library "work" does not contain primary unit "con" File: E:/Altera_Project/My_IP/FreqMeasure/FREQMeasure_WholeSystem.vhd Line: 149
