Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Modelsim & VHDL Configuration

It seems that Modelsim doesn't support VHDL Configuration feature. One of my module contain two architectures, in the top level VHDL file use VHDL configuration to use the two different architectu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I instantiate lots of components using generate clause, pls see below: 

   U2: FOR i IN 0 TO (GEN_TOTAL_CHANNEL - 1) GENERATE
          channel_x: FREQMeasure_SingleChannel GENERIC MAP(GEN_BENCHMARK_FREQUENCE, GEN_MAX_TARGET_FREQUENCE, GEN_MIN_TARGET_FREQUENCE, GEN_T_STROBE_WIDTH)
		     PORT MAP (csi_freqmeasure_benchmark_clock_export, cos_freqmeasure_channel_in_export(i), s_strobe, csi_freqmeasure_clock_reset_n, s_A_TargetCounter(i), s_A_BenchCounter(i));
       END GENERATE;

I hope to use the same FREQMeasure_SingleChannel configuration(showed in pre-post).

In this case, how to specificate configuration in the architecture declarative region?

Thanks!