Modelsim & VHDL Configuration

It depends on what you are simulating. Do you have a test bench that instantiates the entity? If so, then you need to change it to instantiate the configuration, e.g.

dut: configuration work.con generic map (...) port map (...);

If you're testbench instantiates a component, you can bind it to the configuration using the configuration specification I gave in my previous post.

If you are simulating the entity directly, my previous post explained that you need to simulate the configuration.