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Altera_Forum's avatar
Altera_Forum
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18 years ago

Modelsim & VHDL Configuration

It seems that Modelsim doesn't support VHDL Configuration feature. One of my module contain two architectures, in the top level VHDL file use VHDL configuration to use the two different architectu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

You need to put the configuration specification in the declarative region for the generate block, e.g. 


U2: FOR i IN 0 TO (GEN_TOTAL_CHANNEL - 1) GENERATE
    FOR channel_x : FREQMeasure_SingleChannel
           use configuration work.con;
    BEGIN
         -- Your instance here  
    end generate;