IO input delay

What paths/nodes are actually failing? Critical info needed here. Show detail from Report Timing.

It is better to not think of them as constraints at all.

Instead they describe a circuit outside of the FPGA and that circuit, coupled with the circuit inside the FPGA, creates a full setup and hold analysis.

set_output_delay -max 0 -clock clk_out [get_ports data_out]

set_output_delay -min 0 -clock clk_out [get_ports data_out]

Looking at output constraint example, let's break down its components:

1. set_output_delay -> There is a register being driven by an FPGA output

2. -clock clk_out -> This register is clocked by our clock clk_out

3. -max/-min 0.0 -> The external delay has a max of 0.0 and min of 0.0

4. [get_ports data_out] -> The register is driven by port data_out

Looking at the schematic format:

We can see a circuit described outside of the FPGA, with a register feeding another register. This is the standard path analysis done on every path inside the FPGA.

Hope that clarify.

Btw, which training material are you referring to?

Regards,

Richard Tan

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side?

Regards,

Richard Tan

HI RichardTanSY_Intel,

Sorry for the late response, I thought I posted it but it probably wasn't sent.

I mainly interested in the input delay, since I'm going to write the data into internal FIFO and use it internally, so I don't really care about the output delay.

The paths that failing for me are those:

Same concern applied to the input delay constraint.

You can checkout the document below for better visualization.

https://www.intel.com/content/www/us/en/docs/programmable/683243/24-1/input-constraints-set-input-delay.html

Do you need help in closing timing? If so, to better understand and troubleshoot the timing failure, it would be really helpful to have a look at your design files in .qar format (Project > Archive Project) .

Could you please share them with me?

Regards,

Richard Tan

Your report screenshot is unfortunately cutting off why you have a huge data delay of over 6 ns internal to the device. Scroll down that data arrival path to show what's causing that massive delay.

Also, for the edge aligned case, you have to use a PLL to shift the incoming clock appropriately, which does not appear to be the case with your design. You should pretty much always use a PLL whether you are edge or center aligned because the source synchronous PLL compensation mode makes it much easier to meet timing.

Hi,

Could you share the project?

Regards,

Richard Tan

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Best Regards,

Richard Tan