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Yoni_CMT
New Contributor
New ContributorIO input delay
I'm going over the Constraining Source Synchronous Interfaces training and running a very simple design to test myself. I'm trying both center aligned and edge aligned data in the design(with ...
Yoni_CMTNew Contributor
New ContributorHI RichardTanSY_Intel,
Sorry for the late response, I thought I posted it but it probably wasn't sent.
I mainly interested in the input delay, since I'm going to write the data into internal FIFO and use it internally, so I don't really care about the output delay.
The paths that failing for me are those:
