IO input delay

It is better to not think of them as constraints at all.

Instead they describe a circuit outside of the FPGA and that circuit, coupled with the circuit inside the FPGA, creates a full setup and hold analysis.

set_output_delay -max 0 -clock clk_out [get_ports data_out]

set_output_delay -min 0 -clock clk_out [get_ports data_out]

Looking at output constraint example, let's break down its components:

1. set_output_delay -> There is a register being driven by an FPGA output

2. -clock clk_out -> This register is clocked by our clock clk_out

3. -max/-min 0.0 -> The external delay has a max of 0.0 and min of 0.0

4. [get_ports data_out] -> The register is driven by port data_out

Looking at the schematic format:

We can see a circuit described outside of the FPGA, with a register feeding another register. This is the standard path analysis done on every path inside the FPGA.

Hope that clarify.

Btw, which training material are you referring to?

Regards,

Richard Tan