IO input delay

Your report screenshot is unfortunately cutting off why you have a huge data delay of over 6 ns internal to the device. Scroll down that data arrival path to show what's causing that massive delay.

Also, for the edge aligned case, you have to use a PLL to shift the incoming clock appropriately, which does not appear to be the case with your design. You should pretty much always use a PLL whether you are edge or center aligned because the source synchronous PLL compensation mode makes it much easier to meet timing.