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Altera_Forum
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10 years ago

Inserting SignalTap without re-routing design

I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signal tap .stp file to the project and capture some post-fit signals while maintaining the existing placement and routing given that the project is not currently set up for incremental compile? Does smart compilation work for this or will it recompile the design and re-run place-&-route on everything?

Regards, GMM

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Smart Recompile just skips modules if they're unnecessary. It's not very useful.

    You always have a partition called Top, so just set that to Post-Fit. By default, Signal-Tap is put into its own partition and therefore won't affect Top. You need to tap post-fit nodes though.

    (Also, if you're able to try Rapid Recompile, that is supposed to work in this case too, preserving as much of the design as it can)
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Ok, thanks for the response. I tried creating post-fit partition on Top, but when I compiled, I got a message warning that the previously generated Fitter netlist for partition "Top" does not exist. I believe it then used the previously generated synthesis netlist. After the recompile (that ran place & route again which I was hoping to avoid), subsequent compiles after that did recognize the "Top" post-fit netlist and didn't place & route again. I guess the post-fit netlist with full incremental compile enabled needs to have been generated before it will avoid doing place and route again. If adding a SignalTap .stp file to the project at this point, I'm assuming Incremental Compilation needs to be enabled (checked) for the SignalTap instance, but I'm confused as to how this relates to the incremental compile done for the partitions. Does this mean the routes & memories added for signalTap will be unchanged assuming nothng in the .stp file has changed from the last compile?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hmm. You should have a Partition called Top automatically, and after compiling a post-fit netlist already exists for it. (I assume Incremental Compilation is on, but it's on by default and you'd have to go out out of your way to turn it off.). Then just set that Top Partition to Post-Fit, add your signaltap, which again is automatically a partition although it won't show up as one in the Partitions Window, but you will see it in the Incremental Compilation sections of the output reports.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Hmm. You should have a Partition called Top automatically, and after compiling a post-fit netlist already exists for it. (I assume Incremental Compilation is on, but it's on by default and you'd have to go out out of your way to turn it off.). Then just set that Top Partition to Post-Fit, add your signaltap, which again is automatically a partition although it won't show up as one in the Partitions Window, but you will see it in the Incremental Compilation sections of the output reports.

    --- Quote End ---

    I believe the problem is the original design settings had incremental compile turned off. I am having to use an old tool version (Quartus 6.0) due to presence of Nios & avalon switch fabric in the design (from past painful experience, I avoided upgrading to a newer tool), so maybe the default is off for that version or the original designer turned it off.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi

    I am working on an FPGA project in which the behavior of the design changes as soon as I add signal tap to it.

    I have a design with some bugs that I am trying to debug. But whenever I tap out signals, I am unable to recreate the issue and I see something very different from what I was seeing without signal tap.

    I am using Quartus 15.0.1. Can someone please explain to me the process of preserving the design while adding signal tap.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Your top-level is in a partition automatically, so:

    1) Make a copy of the design that has the problem, including /db and /incremental_db. (Basically copy the directory with the .qpf/.qsf in it and all sub-directories)

    2) Assignments -> Design Partition Window to open it

    3) Set the Top partition(and any you might have created) to Post-Fit. If you want, you can right click on them and go to Partition Properties and click the option to Ignore Changes in Source Files, in which case they will always be Post-Fit even if you change your source, but this shouldn't be necessary.

    4) Add SignalTap, and be sure to only tap SignalTap: Post Fit nodes. The main thing to look for is registers, as they should be kept and have a name that makes sense.

    5) Compile. SignalTap is its own partition, so it will get synthesized independently and then placed-and-routed around your post-fit partition/s.

    6) Modify SignalTap and repeat until you find the problem.

    7) Be sure to set the partition back to Source or Post-Synthesis and uncheck Ignore Changes in Source if you had checked that.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi

    Thanks for your reply Rysc. I followed your steps and I am still having the same problem.

    My board sits between the host and server and modifies the packets that are exchanged between them. In my original design I am able to set up a tcp connection between the host and server. I have a bug which occurs in application packets that are sent after connection establishment.

    With signal tap added, I am not even able to establish a tcp connection.

    I have some timing failures at 85 and 0 degrees slow corners that I am trying to fix. Could that be the reason for this erratic behavior?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    In the fitter report, if you go to Incremental Compilation, was your design's placement and routing preserved?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi

    No there is 0% requested and achieved for both placement and routing.

    I have followed your steps and checked by compiling twice.

    Could I be doing something wrong? What is the solution?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Something is going wrong, but hard to say. Synthesis and Partition Merge(if it runs) both have reports about Incremental Compilation and might give a clue. For example, analysis and synthesis might say that the design files have changed and resynthesizing, in which case the post-fit wouldn't try to lock anything down.