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Altera_Forum
Honored Contributor
Honored ContributorInserting SignalTap without re-routing design
I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_ForumHonored Contributor
Honored ContributorHmm. You should have a Partition called Top automatically, and after compiling a post-fit netlist already exists for it. (I assume Incremental Compilation is on, but it's on by default and you'd have to go out out of your way to turn it off.). Then just set that Top Partition to Post-Fit, add your signaltap, which again is automatically a partition although it won't show up as one in the Partitions Window, but you will see it in the Incremental Compilation sections of the output reports.
