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Altera_Forum's avatar
Altera_Forum
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10 years ago

Inserting SignalTap without re-routing design

I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Smart Recompile just skips modules if they're unnecessary. It's not very useful.

You always have a partition called Top, so just set that to Post-Fit. By default, Signal-Tap is put into its own partition and therefore won't affect Top. You need to tap post-fit nodes though.

(Also, if you're able to try Rapid Recompile, that is supposed to work in this case too, preserving as much of the design as it can)