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Altera_Forum
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11 years ago

Inserting SignalTap without re-routing design

I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi

Thanks for your reply Rysc. I followed your steps and I am still having the same problem.

My board sits between the host and server and modifies the packets that are exchanged between them. In my original design I am able to set up a tcp connection between the host and server. I have a bug which occurs in application packets that are sent after connection establishment.

With signal tap added, I am not even able to establish a tcp connection.

I have some timing failures at 85 and 0 degrees slow corners that I am trying to fix. Could that be the reason for this erratic behavior?