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Altera_Forum
Honored Contributor
Honored ContributorInserting SignalTap without re-routing design
I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_ForumHonored Contributor
Honored ContributorSomething is going wrong, but hard to say. Synthesis and Partition Merge(if it runs) both have reports about Incremental Compilation and might give a clue. For example, analysis and synthesis might say that the design files have changed and resynthesizing, in which case the post-fit wouldn't try to lock anything down.
