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Altera_Forum
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11 years ago

Inserting SignalTap without re-routing design

I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi

I am working on an FPGA project in which the behavior of the design changes as soon as I add signal tap to it.

I have a design with some bugs that I am trying to debug. But whenever I tap out signals, I am unable to recreate the issue and I see something very different from what I was seeing without signal tap.

I am using Quartus 15.0.1. Can someone please explain to me the process of preserving the design while adding signal tap.

Thanks