Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorInserting SignalTap without re-routing design
I need to examine some internal signals in an existing FPGA design that was not set up for incremental compile (no design partitions specified for incremental compile). Is there a way to add a signa...
Altera_ForumHonored Contributor
Honored ContributorHi
No there is 0% requested and achieved for both placement and routing. I have followed your steps and checked by compiling twice. Could I be doing something wrong? What is the solution?
