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Altera_Forum's avatar
Altera_Forum
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14 years ago

inout Std_logic_vector Signal Test

Hi,

I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice

error output:# ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024kx8.vhd(12): (vcom-1136) Unknown identifier "std_logic_vector".

vhdl code: 


             entity test_sram1024x8 is
Line 12    PORT ( D    : inout Std_logic_vector(7 downto 0));
             end;
architecture test of test_sram1024x8 is
COMPONENT sram1024x8
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
END COMPONENT ;
SIGNAL A   : bit := '0';
SIGNAL nCE : bit := '1';
SIGNAL nCE2   : bit := '1';
SIGNAL nWE : bit := '1';
SIGNAL nOE : bit := '0';
begin
dut : sram1024x8 
   PORT MAP (
    A => A,
    D => D,
    nCE => nCE,
    nCE2 => nCE2,
    nWE => nWE,
    nOE => nOE );
   
--clock : PROCESS
   --begin
   --wait for 10 ns; clk  <= not clk;
--end PROCESS clock;
stimulus : PROCESS
   begin
   --A <= '1';
   wait for 5 ns; nCE   <= '0';
   wait for 5 ns; nCE2  <= '0';
   wait for 5 ns; nOE  <= '1';
   wait for 12 ns; nWE  <= '0';
   wait;
end PROCESS stimulus;
end test;

20 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    you have probably forgotten to include thse lines:

    library ieee;

    use ieee.std_logic_1164.all;
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I also notice you're trying to map bits to std_logic - you cannot do that. You will have to type convert them.

    Alternatively, dont use the bit type - use std_logic(_vector)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you for your response

    I already use library ieee;use ieee.std_logic_1164.all; within my main component.

    And I insert it again inside the current testbench and get the same error.

    So which ccommand should I use to avoid inout std_logic_vector so that I could run my testbench?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I insert it again inside the current testbench and get the same error.

    --- Quote End ---

    Doesn't sound reasonable, please show the full text. Or it would be a case of mixed-up Modelsim configuration with missing IEEE libraries.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ok here are my 2 files(vhdl Component + Testbench).

    Just take a look.

    sram1024kx8.vhd 

    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sram1024kx8 is
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
end;
architecture Behaviour of sram1024kx8 is
    subtype Byte is Std_logic_vector(7 downto 0);
    type Mem is array (0 to 1048576 ) of byte;
    signal Memory: Mem := (others => Byte'(others=>'U'));
begin
  process(A, D, nCE, nCE2, nWE, nOE)
  begin
    D <= (others => 'Z');
    if nCE='0' and nCE2='0' then
      if nOE = '0' then                  -- Read operation
        D <= Memory(To_Integer(unsigned(A))) after 10 ns;
      elsif nWE = '0' then               -- Write operation
        Memory(To_Integer(unsigned(A))) <= D;
      end if;
    end if;
  end process;
end;

    and tsram1024kx8.vhd as testbench 

    
library ieee;
use ieee.std_logic_1164.all;
entity test_sram1024x8 is
    PORT ( D    : inout Std_logic_vector(7 downto 0));
end;
architecture test of test_sram1024x8 is
COMPONENT sram1024x8
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
END COMPONENT ;
SIGNAL A   : bit := '0';
SIGNAL nCE : bit := '1';
SIGNAL nCE2   : bit := '1';
SIGNAL nWE : bit := '1';
SIGNAL nOE : bit := '0';
begin
dut : sram1024x8 
   PORT MAP (
    A => A,
    D => D,
    nCE => nCE,
    nCE2 => nCE2,
    nWE => nWE,
    nOE => nOE );
   
--clock : PROCESS
   --begin
   --wait for 10 ns; clk  <= not clk;
--end PROCESS clock;
stimulus : PROCESS
   begin
   --A <= '1';
   wait for 5 ns; nCE   <= '0';
   wait for 5 ns; nCE2  <= '0';
   wait for 5 ns; nOE  <= '1';
   wait for 12 ns; nWE  <= '0';
   wait;
end PROCESS stimulus;
end test;
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    compiles fine for me, except for the bit and std_logic incompatability I posted about earlier.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I don't really find out what is the Problem?

    --- Quote End ---

    If you're refering to the std_logic_vector not existing problem - then that is a setup problem on your system. The likelyhood is that you have somhow broken the std_logic_1164 package.

    The other problem is a problem with your code because you have tried to assign a "bit" to a std_logic_vector. You cant do that because of VHDL's strong typing. You have two options to fix it.

    1. Replace all bit(_vector) with std_logic_vector

    2. use the to_std_ulogic/to_std_logic_vector conversion functions in the port map.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Now it compil without problem.

    Just the error with inout std_logic_vector as follow:

    # ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024x8.vhd(38): Signal "a" is type std.standard.bit; expecting type ieee.std_logic_1164.std_logic_vector.

    I will try your advice and see if I can move forward
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi,

    I fixed all errors but one is still there.

    Please any advice for that?

    persistance error

    # ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024x8.vhd(38): Array type for 'a' is not constrained.

    code 

    
library ieee;
use ieee.std_logic_1164.all;
entity test_sram1024x8 is
    PORT ( D    : inout Std_logic_vector(7 downto 0));
end;
architecture test of test_sram1024x8 is
COMPONENT sram1024x8
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
END COMPONENT ;
--------------------------------------
--signal A : Bit_vector(19 downto 0);
--A <= ('0', others => '1');             -- 3
--DataBus <= DataBus(6 downto 0) & DataBus(7); -- 4
--DataBus <= "01110001";     
---------------------------------------
--SIGNAL A   : Std_bit_vector := "00000000000000000000"; 
-- Type T_Data is array (19 downto 0) of std_logic;
SIGNAL A: Std_logic_vector:="00000000000000000000";
SIGNAL nCE : std_logic := '1';
SIGNAL nCE2   : std_logic := '1';
SIGNAL nWE : std_logic := '1';
SIGNAL nOE : std_logic := '0';
begin
dut : sram1024x8 
   PORT MAP (
    A => A,
    D => D,
    nCE => nCE,
    nCE2 => nCE2,
    nWE => nWE,
    nOE => nOE );
   
--clock : PROCESS
   --begin
   --wait for 10 ns; clk  <= not clk;
--end PROCESS clock;
stimulus : PROCESS
   begin
   --A <= '1';
   wait for 5 ns; nCE   <= '0';
   wait for 5 ns; nCE2  <= '0';
   wait for 5 ns; nOE  <= '1';
   wait for 12 ns; nWE  <= '0';
   wait;
end PROCESS stimulus;
end test;