Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

inout Std_logic_vector Signal Test

Hi, I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice error output:# ** Error: Z:/Prototyp/Develo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Now it compil without problem.

Just the error with inout std_logic_vector as follow:

# ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024x8.vhd(38): Signal "a" is type std.standard.bit; expecting type ieee.std_logic_1164.std_logic_vector.

I will try your advice and see if I can move forward