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Altera_Forum
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14 years ago

inout Std_logic_vector Signal Test

Hi, I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice error output:# ** Error: Z:/Prototyp/Develo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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I insert it again inside the current testbench and get the same error.

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Doesn't sound reasonable, please show the full text. Or it would be a case of mixed-up Modelsim configuration with missing IEEE libraries.