inout Std_logic_vector Signal Test

Ok here are my 2 files(vhdl Component + Testbench).

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sram1024kx8 is
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
end;
architecture Behaviour of sram1024kx8 is
    subtype Byte is Std_logic_vector(7 downto 0);
    type Mem is array (0 to 1048576 ) of byte;
    signal Memory: Mem := (others => Byte'(others=>'U'));
begin
  process(A, D, nCE, nCE2, nWE, nOE)
  begin
    D <= (others => 'Z');
    if nCE='0' and nCE2='0' then
      if nOE = '0' then                  -- Read operation
        D <= Memory(To_Integer(unsigned(A))) after 10 ns;
      elsif nWE = '0' then               -- Write operation
        Memory(To_Integer(unsigned(A))) <= D;
      end if;
    end if;
  end process;
end;

library ieee;
use ieee.std_logic_1164.all;
entity test_sram1024x8 is
    PORT ( D    : inout Std_logic_vector(7 downto 0));
end;
architecture test of test_sram1024x8 is
COMPONENT sram1024x8
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
END COMPONENT ;
SIGNAL A   : bit := '0';
SIGNAL nCE : bit := '1';
SIGNAL nCE2   : bit := '1';
SIGNAL nWE : bit := '1';
SIGNAL nOE : bit := '0';
begin
dut : sram1024x8 
   PORT MAP (
    A => A,
    D => D,
    nCE => nCE,
    nCE2 => nCE2,
    nWE => nWE,
    nOE => nOE );
   
--clock : PROCESS
   --begin
   --wait for 10 ns; clk  <= not clk;
--end PROCESS clock;
stimulus : PROCESS
   begin
   --A <= '1';
   wait for 5 ns; nCE   <= '0';
   wait for 5 ns; nCE2  <= '0';
   wait for 5 ns; nOE  <= '1';
   wait for 12 ns; nWE  <= '0';
   wait;
end PROCESS stimulus;
end test;