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I don't really find out what is the Problem?
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If you're refering to the std_logic_vector not existing problem - then that is a setup problem on your system. The likelyhood is that you have somhow broken the std_logic_1164 package.
The other problem is a problem with your code because you have tried to assign a "bit" to a std_logic_vector. You cant do that because of VHDL's strong typing. You have two options to fix it.
1. Replace all bit(_vector) with std_logic_vector
2. use the to_std_ulogic/to_std_logic_vector conversion functions in the port map.
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