inout Std_logic_vector Signal Test

Hi,

I fixed all errors but one is still there.

Please any advice for that?

persistance error

# ** Error: Z:/Prototyp/Development_Infos_Collection/LS4000_Development/HW/FPGA/Tutorial/Simulation/Projects/sram1024kx8/tsram1024x8.vhd(38): Array type for 'a' is not constrained.

code

library ieee;
use ieee.std_logic_1164.all;
entity test_sram1024x8 is
    PORT ( D    : inout Std_logic_vector(7 downto 0));
end;
architecture test of test_sram1024x8 is
COMPONENT sram1024x8
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
END COMPONENT ;
--------------------------------------
--signal A : Bit_vector(19 downto 0);
--A <= ('0', others => '1');             -- 3
--DataBus <= DataBus(6 downto 0) & DataBus(7); -- 4
--DataBus <= "01110001";     
---------------------------------------
--SIGNAL A   : Std_bit_vector := "00000000000000000000"; 
-- Type T_Data is array (19 downto 0) of std_logic;
SIGNAL A: Std_logic_vector:="00000000000000000000";
SIGNAL nCE : std_logic := '1';
SIGNAL nCE2   : std_logic := '1';
SIGNAL nWE : std_logic := '1';
SIGNAL nOE : std_logic := '0';
begin
dut : sram1024x8 
   PORT MAP (
    A => A,
    D => D,
    nCE => nCE,
    nCE2 => nCE2,
    nWE => nWE,
    nOE => nOE );
   
--clock : PROCESS
   --begin
   --wait for 10 ns; clk  <= not clk;
--end PROCESS clock;
stimulus : PROCESS
   begin
   --A <= '1';
   wait for 5 ns; nCE   <= '0';
   wait for 5 ns; nCE2  <= '0';
   wait for 5 ns; nOE  <= '1';
   wait for 12 ns; nWE  <= '0';
   wait;
end PROCESS stimulus;
end test;