Inferred RAM: Pass-through logic generated despite no_rw_check

You should observe your RTL diagram to find answer.

• only one read is specified in the case that the two read addresses are the same

• it should be clear that read and write are mutually exclusive in logic

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity registers is
    Port(
        I_clk: in std_logic;
        I_en: in std_logic;
        I_op: in std_logic_vector(1 downto 0);
        I_selS1: in std_logic_vector(4 downto 0);
        I_selS2: in std_logic_vector(4 downto 0);
        I_selD: in std_logic_vector(4 downto 0);
        I_dataAlu: in std_logic_vector(XLEN-1 downto 0);
        I_dataMem: in std_logic_vector(XLEN-1 downto 0);
        O_dataS1: out std_logic_vector(XLEN-1 downto 0);
        O_dataS2: out std_logic_vector(XLEN-1 downto 0)
    );
end registers;
architecture Behavioral of registers is
    type store_t is array(1 to 31) of std_logic_vector(XLEN-1 downto 0);
    signal regs: store_t := (others => X"00000000");
    attribute ramstyle : string;
    attribute ramstyle of regs : signal is "no_rw_check"; -- why does Quartus still add pass-through logic?
begin
    process(I_clk)
        variable data: std_logic_vector(XLEN-1 downto 0);
    begin
        if rising_edge(I_clk) and I_en = '1' then
            -- TODO: find out why synthesis sees read-during-write behavior
            
            if I_op = REGOP_READ then
                -- we read, we don't write!
                if I_selS1 = I_selS2 then
                    -- both selects address same location
                    -- avoid reading same address twice
                    if I_selS1 = R0 then
                        data := X"00000000";
                    else
                        data := regs(to_integer(unsigned(I_selS1)));
                    end if;
                    O_dataS1 <= data;
                    O_dataS2 <= data;
                else
                    -- two different locations selected for reading
                    -- dual port memory should handle that just fine
                    if I_selS1 = R0 then
                        O_dataS1 <= X"00000000";
                    else
                        O_dataS1 <= regs(to_integer(unsigned(I_selS1)));
                    end if;
                    
                    if I_selS2 = R0 then
                        O_dataS2 <= X"00000000";
                    else
                        O_dataS2 <= regs(to_integer(unsigned(I_selS2)));
                    end if;
                end if;
            
            elsif I_op = REGOP_WRITE_ALU then
                -- we write data from ALU (no read involved)
                if I_selD /= R0 then
                    regs(to_integer(unsigned(I_selD))) <= I_dataAlu;
                end if;
            
            elsif I_op = REGOP_WRITE_MEM then
                -- we write data from memory (no read involved)
                if I_selD /= R0 then
                    regs(to_integer(unsigned(I_selD))) <= I_dataMem;
                end if;
            
            end if;
    
        end if;
    end process;
end Behavioral;

READ_DURING_WRITE_MODE_MIXED_PORTS    OLD_DATA                           Untyped    36
READ_DURING_WRITE_MODE_PORT_A             NEW_DATA_NO_NBE_READ    Untyped    37
READ_DURING_WRITE_MODE_PORT_B             NEW_DATA_NO_NBE_READ    Untyped    38

you need solve that iseld and isels signals different in write and read operation

You can split read and write in two if statement. So they are parallel. But in your code they are in one statement

As you are doing the read in a clock process, I agree that your code shouldn't generate a memory with new read-during-write behaviour. But the code you posted here differs from the recommended altera hdl styles (https://documentation.altera.com/#/00030683-aa$nt00064438) and it's hard to predict how the synthesis tool will implement this. Sometimes it can do some really crazy stuff, and different stuff with different versions. I would recommend instead to make an entity that sticks as much as possible to the recommended style and put your own wrapper logic around it: (you can put both read/write accesses in the same process and avoid using a shared variable if you want though, it works with all the Quartus versions that I tried):

library ieee;
use ieee.std_logic_1164.all;
entity true_dual_port_ram_single_clock is
	generic (
		DATA_WIDTH : natural := 8;
		ADDR_WIDTH : natural := 6
	);
	port (
		clk	: in std_logic;
		addr_a	: in natural range 0 to 2**ADDR_WIDTH - 1;
		addr_b	: in natural range 0 to 2**ADDR_WIDTH - 1;
		data_a	: in std_logic_vector((DATA_WIDTH-1) downto 0);
		data_b	: in std_logic_vector((DATA_WIDTH-1) downto 0);
		we_a	: in std_logic := '1';
		we_b	: in std_logic := '1';
		q_a	: out std_logic_vector((DATA_WIDTH -1) downto 0);
		q_b	: out std_logic_vector((DATA_WIDTH -1) downto 0)
	);
end true_dual_port_ram_single_clock;
architecture rtl of true_dual_port_ram_single_clock is
	-- Build a 2-D array type for the RAM
	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
	type memory_t is array((2**ADDR_WIDTH - 1) downto 0) of word_t;
	-- Declare the RAM signal.	
	shared variable ram : memory_t;
begin
	process(clk)
	begin
	if(rising_edge(clk)) then -- Port A
		if(we_a = '1') then
			ram(addr_a) <= data_a;
			-- Read-during-write on the same port returns NEW data
			q_a <= data_a;
		else 
			-- Read-during-write on the mixed port returns OLD data
			q_a <= ram(addr_a);
		end if;
	end if;
	end process;
	process(clk)
	begin
	if(rising_edge(clk)) then -- Port B 
		if(we_b = '1') then
			ram(addr_b) := data_b;
			-- Read-during-write on the same port returns NEW data
			q_b <= data_b;
		else 
			-- Read-during-write on the mixed port returns OLD data
			q_b <= ram(addr_b);
		end if;
	end if;
	end process;
end rtl;

Thank you both for your responses!

While it doesnt match the coding style in the guildlines, quartus is normally very good at recognising rams from code that doesnt quite match the guidelines.

Thanks to the forum input I was now able to construct a solution that is recognized as not needing pass-through logic:

library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity registers is
    Port(
        I_clk: in std_logic;
        I_en: in std_logic;
        I_op: in std_logic_vector(1 downto 0);
        I_selS1: in std_logic_vector(4 downto 0);
        I_selS2: in std_logic_vector(4 downto 0);
        I_selD: in std_logic_vector(4 downto 0);
        I_dataAlu: in std_logic_vector(XLEN-1 downto 0);
        I_dataMem: in std_logic_vector(XLEN-1 downto 0);
        O_dataS1: out std_logic_vector(XLEN-1 downto 0);
        O_dataS2: out std_logic_vector(XLEN-1 downto 0)
    );
end registers;
architecture Behavioral of registers is
    type store_t is array(0 to 31) of std_logic_vector(XLEN-1 downto 0);
    signal regs: store_t := (others => X"00000000");
    attribute ramstyle : string;
    attribute ramstyle of regs : signal is "no_rw_check";
begin
    -----------------------------------
    -- first port of dual-port RAM
    -- used for one read or one write
    -----------------------------------
    process(I_clk)
        variable write_enabled: boolean;
        variable data: std_logic_vector(XLEN-1 downto 0);
    begin
        if rising_edge(I_clk) and I_en = '1' then
            data := X"00000000";
            -- by default assume read access
            write_enabled := false;
            -- determine details of write operations
            case I_op is
            
                when REGOP_WRITE_ALU =>
                    -- write to destination register
                    write_enabled := true;
                    if I_selD /= R0 then
                        data := I_dataAlu;
                    end if;
                
                when REGOP_WRITE_MEM =>
                    -- write to destination register
                    write_enabled := true;
                    if I_selD /= R0 then
                        data := I_dataMem;
                    end if;
                
                when others =>
                    null;
            end case;
            -- this is a pattern that Quartus RAM synthesis understands
            -- as *not* being read-during-write (with no_rw_check attribute)
            if write_enabled then
                regs(to_integer(unsigned(I_selD))) <= data;
            else
                O_dataS1 <= regs(to_integer(unsigned(I_selS1)));
            end if;
            
    
        end if;
    end process;
    
    --------------------------------
    -- second port of dual port RAM
    -- used only for one read
    --------------------------------
    process(I_clk)
    begin
        if rising_edge(I_clk) and I_en = '1' then
            if I_op = REGOP_READ then
                O_dataS2 <= regs(to_integer(unsigned(I_selS2)));
            end if;
    
        end if;
    end process;
    
end Behavioral;

Well, I can always just try my luck ;)

			-- this is a pattern that Quartus RAM synthesis understands
			-- as *not* being read-during-write (with no_rw_check attribute)
			if write_enabled then
				regs(to_integer(unsigned(I_selD))) <= data;
			else
				O_dataS1 <= regs(to_integer(unsigned(I_selS1)));
				O_dataS2 <= regs(to_integer(unsigned(I_selS2)));
			end if;

if I_selS1 = R0 then
	O_dataS1 <= X"00000000";
end if;