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Altera_Forum
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10 years ago

Inferred RAM: Pass-through logic generated despite no_rw_check

Dear all, I'm a hobbyist currently learning VHDL. My learning vehicle is a self-developed RISC-V CPU that that I develop in the Lite edition of Quartus Prime 15.1. The CPU is working fine alrea...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Thank you both for your responses!

I'm glad that the issue at hand apparently is merely caused by a coding style mismatch and not by a severe misunderstanding on my side regarding VHDL semantics. I will try to express the desired behavior in a way that conforms more to the recommended coding style.

Best regards,

Maik