Inferred RAM: Pass-through logic generated despite no_rw_check

Well, I can always just try my luck ;)

Btw, it turns out that in my case the second process is not needed, instead I can have the two read accesses in the same process:

			-- this is a pattern that Quartus RAM synthesis understands
			-- as *not* being read-during-write (with no_rw_check attribute)
			if write_enabled then
				regs(to_integer(unsigned(I_selD))) <= data;
			else
				O_dataS1 <= regs(to_integer(unsigned(I_selS1)));
				O_dataS2 <= regs(to_integer(unsigned(I_selS2)));
			end if;

What *is* important: There apparently can be only one assignment to the output signals for RAM contents. If one includes, e.g., something like

if I_selS1 = R0 then
	O_dataS1 <= X"00000000";
end if;

somewhere (to ensure that reads on CPU register 0 always returns zero) Quartus will include the pass-through logic, no matter if no_rw_check is there or not. Instead I currently live with address 0 actually being a memory location, initializing it with zero and never allowing anything but zero to be written there.