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Altera_Forum
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10 years ago

Inferred RAM: Pass-through logic generated despite no_rw_check

Dear all, I'm a hobbyist currently learning VHDL. My learning vehicle is a self-developed RISC-V CPU that that I develop in the Lite edition of Quartus Prime 15.1. The CPU is working fine alrea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You should observe your RTL diagram to find answer.

if I were you: (brainstorm, suggestions)

1)try out make only one assignment to ram.

2)your read two addresses . Are both really needed in the same time? if not, you should read ram only once.

3)it seems tool believes that iseld and isels1, isels2 could be the same.

Using attribute for assignments implied from code sometimes bring another attribute . please check Analysis&Synthesis report for additional signal attribute that comes together.