I am getting compiling error when I use Shift Right logic in VHDL by Quartus 6.2

Hello,

to avoid speculative guesses, can you please tell the complete signal definitions and library uses.

Generally the said error is reported when an overloaded operator or function isn't unique in a given context, e. g. when a * could be either signed or unsigned. This can be somewhat annoying.

Regards,

Frank

Hello,

I normally use explicite bit assignments instead of shift operaters in VHDL, e. g.

shiftreg <= '0' & shiftreg(shiftreg'left downto 1); -- right shift

Regards,

Frank

Thanks Brad and Frank for your quick response.

I am very junior to use VHDL please simplify the solutions for me! :o

well, Frank, is that mean I need to add the line that your wrote to my code Vs what I have? Do I need to assign or set wire or reg for that?

Here is more part of my code that may help for debugging: (I may drop some stuff from copy and past of the code, but you know what I mean ) Very appreciated for your help and advance. Thanks.-Negar

------------------------- Library and Package Bindings -------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

------------------------------ Entity Declaration ------------------------------

entity VID_PLD is

port (

--

-- Clock(s)

--

C_HKSCLK_VID : in std_logic; -- 33MHz Clock should be up & running by now

C_VID_SLOW_CLK : in std_logic; -- Note: susclk is availible 100ms + 8 RTC clks

-- after NB_RSMRST_N

-- Reset(s)

--

C_VID_PWROK : in std_logic; -- GCLRn: Pwr_Rst dependent rails stable (min 350 ms)

--

-- Other PowerGood / PWROK / Ready / VTT_PWRGD Signals

--

C_PVRM_PWROK : in std_logic;

G_GFX_VID : in std_logic_vector(7 downto 0);

G_VIDOUT : out std_logic_vector(7 downto 0);

G_GFX_VIDOUT : out std_logic_vector(7 downto 0);

C_MB_OVRR_N :in std_logic;

C_RST_VID_S1 : in std_logic;

signal VIDOUT : std_logic_vector(7 downto 0);

signal VIDOUT1 : std_logic_vector(7 downto 0);

signal VIDOUT2 : std_logic_vector(7 downto 0);

signal GFX_VIDOUT : std_logic_vector(7 downto 0); --added for GFX VID.--NR

signal GFX_VIDOUT1 : std_logic_vector(7 downto 0);

signal GFX_VIDOUT2 : std_logic_vector(7 downto 0);

MBDTVIDOUT : process (C_RST_VID_S1, C_MB_OVRR_N)

begin

if (C_RST_VID_S1 ='0') then

GFX_VIDOUT <= GFX_VIDOUT1;

VIDOUT <= VIDOUT ;

elsif (C_MB_OVRR_N ='0') then ---MB mode-->CPU-VID table need to be change

VIDOUT <= VIDOUT1(7 downto 0)-"00010010" ; -- ( -12h)

VIDOUT <= VIDOUT2 srl 1; --NR:I need to shift 1 bit to right but has syntx error-

GFX_VIDOUT <= GFX_VIDOUT1;

elsif (C_MB_OVRR_N ='1') then ---DT mode-->GFX Table need to be change

VIDOUT <= VIDOUT1;

GFX_VIDOUT2 <= GFX_VIDOUT1 sll 1; --NR:I need to shift 1 bit to left but has syntx error

GFX_VIDOUT <= GFX_VIDOUT1(7 downto 0)+"00010010"; -- (+ 12h)

end if;

end process;

--- Quote Start ---

I am very junior to use VHDL please simplify the solutions for me!

--- Quote End ---

I like Frank's solution, but if you want to stick with the shift operator you might be able to find some type conversion help in a VHDL book. I don't do that in VHDL often enough to remember how without experimenting or looking it up each time. Sometimes you can do a direct type conversion (for example, "integer(3.6)" converts the real number to an integer). Because you are using std_logic_vector, however, you might have to find a function that does the conversion. I never remember what conversion functions are available and have to search for an example when I need them.

Hello,

from your posted code, I could see the problem.

It's common, to use STD_LOGIC_VECTOR for signals, that's represent actually numerical data. One reason is, that the VHDL declaration of many Altera Megafunctions requires it. Also, the STD_LOGIC_VECTOR is the type best corresponding to the nature of signals at the FPGA's external interface.

If you wan't to carry out numerical operations on a signal (as you do with your substraction), than you must use numerical types. Your solution is to import STD_LOGIC_UNSIGNED library that effectively treats all STD_LOGIC_VECTOR signals optionally as unsigned. Personally, I prefer explicite defintion of UNSIGNED respectively SIGNED signals and type conversion where necessary. But that's a matter of coding style (or flavour).

The point is, that different collections of VHDL libraries can be used, defining different operators and functions, some of them mutual exclusive. As a simple example, STD_LOGIC_UNSIGNED and STD_LOGIC_SIGNED can't be in effect at the same time, nor can't NUMERIC_STD. It is instructive, to interrogate which operators and functions are supplied by the imported libraries, these are the respective library files referenced in your design:

use IEEE.STD_LOGIC_1164.ALL; -- vhdl\ieee\std_1164.vhd

use IEEE.STD_LOGIC_ARITH.ALL; -- vhdl\synopsys\syn_arit.vhd

use IEEE.STD_LOGIC_UNSIGNED.ALL; -- vhdl\synopsys\syn_unsi.vhd

You will see, that none of the libraries define srl or sll as an operator. This is done in IEEE.NUMERIC_STD, but not for STD_LOGIC_VECTOR signals. However, STD_LOGIC_UNSIGNED library has a similar function that could be used:

  VIDOUT <= SHR(VIDOUT2,"1"); --NR:I need to shift 1 bit to right 
  GFX_VIDOUT2 <= SHL(GFX_VIDOUT1,"1"); --NR:I need to shift 1 bit to left

These functions don't allow operator usage and have a STD_LOGIC_VECTOR shift count.

Or use the syntax I suggested

  VIDOUT <= '0' & VIDOUT2(7 downto 1);
  GFX_VIDOUT2 <= GFX_VIDOUT1(6 downto 0) & '0';

The advantage with this construct is, to my opinion, that you explicitely define what is shifted-in or out.

Regards,

Frank

When in doubt, look at the packages under quartus/libraries/vhdl! The VHDL language only pre-defines srl, sll, sra, sla, ror, rol when the left operand is an array of the std.standard.boolean or std.standard.bit and the right operand is an integer type or subtype. If you declared your signals with type bit_vector and not std_logic_vector, you'd be OK. ieee.std_logic_arith defines:

function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;

function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;

function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;

function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;

Note the lack of support for integer on the right operand. You'd need to use conv_unsigned(1, 1) to convert 1 into the equivalent "unsigned" type value.

I prefer to use ieee.numeric_std over ieee.std_logic_arith. It defines sll, srl, ror, and rol for unsigned/signed left operands and integer right operands.

Well, I already got my coffee this morning...

Best regards,

Frank