Honored Contributor
Honored ContributorHello,
from your posted code, I could see the problem. It's common, to use STD_LOGIC_VECTOR for signals, that's represent actually numerical data. One reason is, that the VHDL declaration of many Altera Megafunctions requires it. Also, the STD_LOGIC_VECTOR is the type best corresponding to the nature of signals at the FPGA's external interface. If you wan't to carry out numerical operations on a signal (as you do with your substraction), than you must use numerical types. Your solution is to import STD_LOGIC_UNSIGNED library that effectively treats all STD_LOGIC_VECTOR signals optionally as unsigned. Personally, I prefer explicite defintion of UNSIGNED respectively SIGNED signals and type conversion where necessary. But that's a matter of coding style (or flavour). The point is, that different collections of VHDL libraries can be used, defining different operators and functions, some of them mutual exclusive. As a simple example, STD_LOGIC_UNSIGNED and STD_LOGIC_SIGNED can't be in effect at the same time, nor can't NUMERIC_STD. It is instructive, to interrogate which operators and functions are supplied by the imported libraries, these are the respective library files referenced in your design: use IEEE.STD_LOGIC_1164.ALL; -- vhdl\ieee\std_1164.vhd use IEEE.STD_LOGIC_ARITH.ALL; -- vhdl\synopsys\syn_arit.vhd use IEEE.STD_LOGIC_UNSIGNED.ALL; -- vhdl\synopsys\syn_unsi.vhd You will see, that none of the libraries define srl or sll as an operator. This is done in IEEE.NUMERIC_STD, but not for STD_LOGIC_VECTOR signals. However, STD_LOGIC_UNSIGNED library has a similar function that could be used: VIDOUT <= SHR(VIDOUT2,"1"); --NR:I need to shift 1 bit to right
GFX_VIDOUT2 <= SHL(GFX_VIDOUT1,"1"); --NR:I need to shift 1 bit to left VIDOUT <= '0' & VIDOUT2(7 downto 1);
GFX_VIDOUT2 <= GFX_VIDOUT1(6 downto 0) & '0';
