Hi I am getting compiling error "can not determine defination of operation" when I am using shift right or shift left logic command in VHDL by Quartus-II tools rev6.2. :confused: is anybody can help me please? the command is correct based in VHDL code: VIDOUT <= VIDOUT2 srl 1; GFX_VIDOUT <= GFX_VIDOUT1; Thanks. -NR

Hello, to avoid speculative guesses, can you please tell the complete signal definitions and library uses. Generally the said error is reported when an overloaded operator or function isn't unique in a given context, e. g. when a * could be either signed or unsigned. This can be somewhat annoying. Regards, Frank

I have a VHDL reference that says the shift operators are not provided in VHDL-87, but Quartus II version 7.2 synthesizes the srl operator for me with no complaint with either VHDL87 or VHDL93 selected.

Because of Frank's post, I changed to std_logic_vector. I got the error for that. You might need to do some type casting to use a type supported by srl.

Hello, I normally use explicite bit assignments instead of shift operaters in VHDL, e. g. shiftreg <= '0' & shiftreg(shiftreg'left downto 1); -- right shift Regards, Frank

Thanks Brad and Frank for your quick response. I am very junior to use VHDL please simplify the solutions for me! :o well, Frank, is that mean I need to add the line that your wrote to my code Vs what I have? Do I need to assign or set wire or reg for that? Here is more part of my code that may help for debugging: (I may drop some stuff from copy and past of the code, but you know what I mean ) Very appreciated for your help and advance. Thanks.-Negar ------------------------- Library and Package Bindings ------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------ Entity Declaration ------------------------------ entity VID_PLD is port ( -- -- Clock(s) -- C_HKSCLK_VID : in std_logic; -- 33MHz Clock should be up & running by now C_VID_SLOW_CLK : in std_logic; -- Note: susclk is availible 100ms + 8 RTC clks -- after NB_RSMRST_N -- Reset(s) -- C_VID_PWROK : in std_logic; -- GCLRn: Pwr_Rst dependent rails stable (min 350 ms) -- -- Other PowerGood / PWROK / Ready / VTT_PWRGD Signals -- C_PVRM_PWROK : in std_logic; G_GFX_VID : in std_logic_vector(7 downto 0); G_VIDOUT : out std_logic_vector(7 downto 0); G_GFX_VIDOUT : out std_logic_vector(7 downto 0); C_MB_OVRR_N :in std_logic; C_RST_VID_S1 : in std_logic; signal VIDOUT : std_logic_vector(7 downto 0); signal VIDOUT1 : std_logic_vector(7 downto 0); signal VIDOUT2 : std_logic_vector(7 downto 0); signal GFX_VIDOUT : std_logic_vector(7 downto 0); --added for GFX VID.--NR signal GFX_VIDOUT1 : std_logic_vector(7 downto 0); signal GFX_VIDOUT2 : std_logic_vector(7 downto 0); MBDTVIDOUT : process (C_RST_VID_S1, C_MB_OVRR_N) begin if (C_RST_VID_S1 ='0') then GFX_VIDOUT <= GFX_VIDOUT1; VIDOUT <= VIDOUT ; elsif (C_MB_OVRR_N ='0') then ---MB mode-->CPU-VID table need to be change VIDOUT <= VIDOUT1(7 downto 0)-"00010010" ; -- ( -12h) VIDOUT <= VIDOUT2 srl 1; --NR:I need to shift 1 bit to right but has syntx error- GFX_VIDOUT <= GFX_VIDOUT1; elsif (C_MB_OVRR_N ='1') then ---DT mode-->GFX Table need to be change VIDOUT <= VIDOUT1; GFX_VIDOUT2 <= GFX_VIDOUT1 sll 1; --NR:I need to shift 1 bit to left but has syntx error GFX_VIDOUT <= GFX_VIDOUT1(7 downto 0)+"00010010"; -- (+ 12h) end if; end process;

I am getting compiling error when I use Shift Right logic in VHDL by Quartus 6.2

15 Replies

Altera_Forum
Honored Contributor
18 years ago
I love all of you ：）
Altera_Forum
Honored Contributor
18 years ago
--- Quote Start ---
Because of Frank's post, I changed to std_logic_vector. I got the error for that.
--- Quote End ---

Thanks, Frank and HDL Guru, for explaining the package part of this. I created my test case from a text editor template and didn't think to check the packages when I changed to std_logic_vector.
Altera_Forum
Honored Contributor
18 years ago
Oh you made my day, :) thanks a lot. Please let me update my code and run it again to see if I can compile or not, I'll update you soon.
Thanks again,
-Negar
Altera_Forum
Honored Contributor
18 years ago
Thanks Frank, Brad and all,
I used Frank's suggested code lines and did work with my STD_LOGIC_UNSIGNED. I could compile the code with no errors. I will do a small simulation later on to see my shifted data.
Thanks again and you guys are awesome.
What a nice web page is!
-Negar
Altera_Forum
Honored Contributor
14 years ago
Yes Frank.. That seems to be the best option when using VHDL.

Regards
Balu

--- Quote Start ---
Hello,

I normally use explicite bit assignments instead of shift operaters in VHDL, e. g.
shiftreg <= '0' & shiftreg(shiftreg'left downto 1); -- right shift

Regards,

Frank
--- Quote End ---

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I am getting compiling error when I use Shift Right logic in VHDL by Quartus 6.2

15 Replies

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