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Altera_Forum
Honored Contributor
18 years agoHello,
I normally use explicite bit assignments instead of shift operaters in VHDL, e. g.shiftreg <= '0' & shiftreg(shiftreg'left downto 1); -- right shift Regards, FrankHello,
I normally use explicite bit assignments instead of shift operaters in VHDL, e. g.shiftreg <= '0' & shiftreg(shiftreg'left downto 1); -- right shift Regards, Frank