I am getting compiling error when I use Shift Right logic in VHDL by Quartus 6.2

Thanks Brad and Frank for your quick response.

I am very junior to use VHDL please simplify the solutions for me! :o

well, Frank, is that mean I need to add the line that your wrote to my code Vs what I have? Do I need to assign or set wire or reg for that?

Here is more part of my code that may help for debugging: (I may drop some stuff from copy and past of the code, but you know what I mean ) Very appreciated for your help and advance. Thanks.-Negar

------------------------- Library and Package Bindings -------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

------------------------------ Entity Declaration ------------------------------

entity VID_PLD is

port (

--

-- Clock(s)

--

C_HKSCLK_VID : in std_logic; -- 33MHz Clock should be up & running by now

C_VID_SLOW_CLK : in std_logic; -- Note: susclk is availible 100ms + 8 RTC clks

-- after NB_RSMRST_N

-- Reset(s)

--

C_VID_PWROK : in std_logic; -- GCLRn: Pwr_Rst dependent rails stable (min 350 ms)

--

-- Other PowerGood / PWROK / Ready / VTT_PWRGD Signals

--

C_PVRM_PWROK : in std_logic;

G_GFX_VID : in std_logic_vector(7 downto 0);

G_VIDOUT : out std_logic_vector(7 downto 0);

G_GFX_VIDOUT : out std_logic_vector(7 downto 0);

C_MB_OVRR_N :in std_logic;

C_RST_VID_S1 : in std_logic;

signal VIDOUT : std_logic_vector(7 downto 0);

signal VIDOUT1 : std_logic_vector(7 downto 0);

signal VIDOUT2 : std_logic_vector(7 downto 0);

signal GFX_VIDOUT : std_logic_vector(7 downto 0); --added for GFX VID.--NR

signal GFX_VIDOUT1 : std_logic_vector(7 downto 0);

signal GFX_VIDOUT2 : std_logic_vector(7 downto 0);

MBDTVIDOUT : process (C_RST_VID_S1, C_MB_OVRR_N)

begin

if (C_RST_VID_S1 ='0') then

GFX_VIDOUT <= GFX_VIDOUT1;

VIDOUT <= VIDOUT ;

elsif (C_MB_OVRR_N ='0') then ---MB mode-->CPU-VID table need to be change

VIDOUT <= VIDOUT1(7 downto 0)-"00010010" ; -- ( -12h)

VIDOUT <= VIDOUT2 srl 1; --NR:I need to shift 1 bit to right but has syntx error-

GFX_VIDOUT <= GFX_VIDOUT1;

elsif (C_MB_OVRR_N ='1') then ---DT mode-->GFX Table need to be change

VIDOUT <= VIDOUT1;

GFX_VIDOUT2 <= GFX_VIDOUT1 sll 1; --NR:I need to shift 1 bit to left but has syntx error

GFX_VIDOUT <= GFX_VIDOUT1(7 downto 0)+"00010010"; -- (+ 12h)

end if;

end process;