I am getting compiling error when I use Shift Right logic in VHDL by Quartus 6.2

When in doubt, look at the packages under quartus/libraries/vhdl! The VHDL language only pre-defines srl, sll, sra, sla, ror, rol when the left operand is an array of the std.standard.boolean or std.standard.bit and the right operand is an integer type or subtype. If you declared your signals with type bit_vector and not std_logic_vector, you'd be OK. ieee.std_logic_arith defines:

function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;

function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;

function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;

function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;

Note the lack of support for integer on the right operand. You'd need to use conv_unsigned(1, 1) to convert 1 into the equivalent "unsigned" type value.

I prefer to use ieee.numeric_std over ieee.std_logic_arith. It defines sll, srl, ror, and rol for unsigned/signed left operands and integer right operands.