I can add .gpio_x_pad_out_export and .gpio_din_export to HPS Sys, but the Interface Planner only allows pin selection for the Bank 2L GPIO1_IO23..0. It doesn't allow selection of the unused pins of GPIO0_IO11..4. These are unused HPS I/O and need to be assigned to .gpio_x_pad_in & out _export. How is this enabled? Why is unused GPIO1 allowed and not unused GPIO0? Other pins in Bank 2L GPIO0 are used, with the pin multiplexer, for USB1 and UART0. The reset of the pins are not used.

Hi,I understand now, however in your case, in the documentation stated that:There are 48 HPS peripheral pins that are shared with the FPGA core. They are divided into four quadrants of 12 signals per quadrant. Each quadrant can be assigned to the HPS or the FPGA fabric.In each shared I/O quadrant, all 12 I/Os are assigned either to the FPGA or to the HPS. It is not possible to divide the I/Os in a quadrant between the FPGA and HPS.So if you must, you have to have all the HPS' 12 I/Os on one quadrant in order to use the maximum 3 quadrant for FPGA.Reference:https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/shared-i-o-pins.html

HPS unused IO Access on Arria 10 | Altera Community

13 Replies

sstrell
Super Contributor
3 years ago
Can you show your configuration in the HPS parameter editor?
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

Yes, can you share your HPS parameter editor, or share your qsys file.
BTanner
New Contributor
3 years ago
Attached is a doc with images of the HPS parameter editor and the schematic bank with the shared I/O. The zip file contains the qsf file for the project.
Elsa_Pins_top.zip3 KB
intel_issues.docx674 KB
- BTanner
  New Contributor
  3 years ago
  Here is the qsys file.
  HPS_System.zip23 KB
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

Thanks for the files and screenshot.

However, it seems I have issue to look at your qsys file, is it possible that you archive your project.

And also, screenshot your "Arria 10 HPS" Parameters Settings.
BTanner
New Contributor
3 years ago
Thanks for the help.

Here is the project and screen shots of the various Parameter Tabs.
HPS_Parameter.docx263 KB
Elsa_Pins_top_21_4_0_67.qar17.8 MB
sstrell
Super Contributor
3 years ago
If you want finer control of the HPS pin usage, go to the Advanced Pin Placement tab in the parameter editor as seen in your screenshot. By just enabling the peripherals you want like you have, you have no control over their placement.
BTanner
New Contributor
3 years ago
Thanks for that input. I understand about the fixe placement of the HPS peripherals. It is the unused ones, that are free to connect to the FPGA fabric. It is these unused ones where the Interface Planner only allows the placement of these in the GPIO1 pins of the 2L bank and not the GPIO0. The unused (by the HPS) pins of the entire 2L bank are supposed to be assignable to the fpga fabric.
sstrell
Super Contributor
3 years ago
So you're talking about "loaner I/O", allowing the FPGA to use HPS pins. Did you check the Advanced FPGA Placement tab?
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

Any update from your side?

The settings are in the Advanced Pin Placement tabs, in the HPS parameters in the screenshot if you can see. Open that, and set to the GPIO "pin name".
- BTanner
  New Contributor
  3 years ago
  I believe, and it matches with the behavior of Quartus’ Interface Planner, that to assign unused HPS GPIO, from the 2L bank, for connection to the fabric (not HPS) you add the GPIO Intel FPGA IP (they no longer use the term Loaner I/O).
  
  This will provide an I/O connection to the I/O pad and an interface for the FPGA Fabric.
  
  The Interface Planner will allow placement of the pad_in/out only in the Q3 & Q4 I/Os of the 2L bank. It is supposed to allow placement of them in the unused pins of the Q1 & Q2 pins.
  
  The selection of the GPIO in the IP selection on the Advanced Pin Placement, assigns an IO pin to the HPS and not a connection to the fabric.
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

I understand now, however in your case, in the documentation stated that:

There are 48 HPS peripheral pins that are shared with the FPGA core. They are divided into four quadrants of 12 signals per quadrant. Each quadrant can be assigned to the HPS or the FPGA fabric.

In each shared I/O quadrant, all 12 I/Os are assigned either to the FPGA or to the HPS. It is not possible to divide the I/Os in a quadrant between the FPGA and HPS.

So if you must, you have to have all the HPS' 12 I/Os on one quadrant in order to use the maximum 3 quadrant for FPGA.

Reference:
https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/shared-i-o-pins.html
- BTanner
  New Contributor
  3 years ago
  Thank you for the explanation and details.