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BTanner's avatar
BTanner
Icon for New Contributor rankNew Contributor
4 years ago
Solved

HPS unused IO Access on Arria 10

I can add .gpio_x_pad_out_export and .gpio_din_export to HPS Sys, but the Interface Planner only allows pin selection for the Bank 2L GPIO1_IO23..0. It doesn't allow selection of the unused pins of G...
  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    4 years ago

    Hi,


    I understand now, however in your case, in the documentation stated that:


    There are 48 HPS peripheral pins that are shared with the FPGA core. They are divided into four quadrants of 12 signals per quadrant. Each quadrant can be assigned to the HPS or the FPGA fabric.


    In each shared I/O quadrant, all 12 I/Os are assigned either to the FPGA or to the HPS. It is not possible to divide the I/Os in a quadrant between the FPGA and HPS.


    So if you must, you have to have all the HPS' 12 I/Os on one quadrant in order to use the maximum 3 quadrant for FPGA.


    Reference:

    https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/shared-i-o-pins.html


EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Any update from your side?


The settings are in the Advanced Pin Placement tabs, in the HPS parameters in the screenshot if you can see. Open that, and set to the GPIO "pin name".


BTanner's avatar
BTanner
Icon for New Contributor rankNew Contributor
4 years ago

I believe, and it matches with the behavior of Quartus’ Interface Planner, that to assign unused HPS GPIO, from the 2L bank, for connection to the fabric (not HPS) you add the GPIO Intel FPGA IP (they no longer use the term Loaner I/O).

This will provide an I/O connection to the I/O pad and an interface for the FPGA Fabric.

The Interface Planner will allow placement of the pad_in/out only in the Q3 & Q4 I/Os of the 2L bank. It is supposed to allow placement of them in the unused pins of the Q1 & Q2 pins.

The selection of the GPIO in the IP selection on the Advanced Pin Placement, assigns an IO pin to the HPS and not a connection to the fabric.