HPS unused IO Access on Arria 10

Hi,

I understand now, however in your case, in the documentation stated that:

There are 48 HPS peripheral pins that are shared with the FPGA core. They are divided into four quadrants of 12 signals per quadrant. Each quadrant can be assigned to the HPS or the FPGA fabric.

In each shared I/O quadrant, all 12 I/Os are assigned either to the FPGA or to the HPS. It is not possible to divide the I/Os in a quadrant between the FPGA and HPS.

So if you must, you have to have all the HPS' 12 I/Os on one quadrant in order to use the maximum 3 quadrant for FPGA.

Reference:

https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/shared-i-o-pins.html