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BTanner's avatar
BTanner
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4 years ago
Solved

HPS unused IO Access on Arria 10

I can add .gpio_x_pad_out_export and .gpio_din_export to HPS Sys, but the Interface Planner only allows pin selection for the Bank 2L GPIO1_IO23..0. It doesn't allow selection of the unused pins of G...
  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    4 years ago

    Hi,


    I understand now, however in your case, in the documentation stated that:


    There are 48 HPS peripheral pins that are shared with the FPGA core. They are divided into four quadrants of 12 signals per quadrant. Each quadrant can be assigned to the HPS or the FPGA fabric.


    In each shared I/O quadrant, all 12 I/Os are assigned either to the FPGA or to the HPS. It is not possible to divide the I/Os in a quadrant between the FPGA and HPS.


    So if you must, you have to have all the HPS' 12 I/Os on one quadrant in order to use the maximum 3 quadrant for FPGA.


    Reference:

    https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/shared-i-o-pins.html


BTanner's avatar
BTanner
Icon for New Contributor rankNew Contributor
4 years ago

Thanks for that input. I understand about the fixe placement of the HPS peripherals. It is the unused ones, that are free to connect to the FPGA fabric. It is these unused ones where the Interface Planner only allows the placement of these in the GPIO1 pins of the 2L bank and not the GPIO0. The unused (by the HPS) pins of the entire 2L bank are supposed to be assignable to the fpga fabric.