How to write a verilog memory code with a inout data port

my current src:

module mem_test(address, MEM_RW, MEM_OE, MEM_DATA_bidir, clk);

input [7:0] address;

input MEM_RW, MEM_OE;

//mem_oe=1 for memory output enable, mem_oe=0 output=zzzz...

//mem_rw=0 for read, mem_rw=1 for write

inout [17:0] MEM_DATA_bidir;

input clk;

reg [17:0] data_out;

wire [17:0] MEM_DATA;

reg [17:0] Memory [0:255];

wire Read = MEM_OE && (!MEM_RW) ;

wire Write = MEM_OE && MEM_RW ;

assign MEM_DATA_bidir = Read ? data_out : 'z ;

always@(posedge clk) begin

if (Write) Memory[address] <= MEM_DATA_bidir ;

data_out <= Memory[address] ;

end

endmodule

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But anyway I didn't get one clock read operation.

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I don't exactly understand what's going on in your simulation. A RAM with unregistered outputs will send the data after latching the read address, without an additional cycle of delay. You can check in the respective device handbooks. Also your Verilog code is specifying this operation. So the design compiler should either implement or reject it, but not add a delay cycle. Did you perform a functional or timing simulation? What's the involved device, what's the clock frequency?

CycloneIII C7 100Mhz

one clock operation in case if all memory compile in logic registers. not memory.

my simulation on previous page was for memory. and seems to be working fine.

outputs in simulation was not VirtualPins. it cost + several ns to timings

I hope I am expressing myself correctly =)

Thanks you guys. Now I have figured out what's wrong with my original code.

In my original code below, i shouldn't have included MEM_OE condition in the always block. That should only appear with the assign statement. That's kind of a standard way of manipulating this bi-directional port stuff. In this case, the MEM_RW actually represents the select signal for tri-state buffer in the bi-directional port.

assign MEM_DATA=(MEM_OE&&!MEM_RW)?data_out:18'bz;
always@(posedge clk)
begin
  if(!MEM_RW&&MEM_OE)
    data_out<=Memory;  
  else if(MEM_RW&&MEM_OE)
    begin
      Memory<=MEM_DATA;
     
    end

end

you don't need if for data_out assign.

for example in recommended hdl coding styles memory written that:

begin

if (we) mem[write_address] = d;

q = mem[read_address];

end

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bark,

Oh so the read operation has to take two cycles if i want to use memory...

Then how should i modify my verilog code?

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No, the read does not take 2 cycles unless there are registers on memory out or in. In fact there is a way to write and read in the same cycle. You should use the MegaWizard to create the kind of memory that you want. Click on the "Documentation" button to get sample waveforms after you have set the options.

Also the memory does not have tri-state drivers but you can hang any driver type on the memory output then have total control of the gating,

The memory latches the inputs at clock time, but if you also register the input there will be a cycle delay.