How to write a verilog memory code with a inout data port

Thanks you guys. Now I have figured out what's wrong with my original code.

In my original code below, i shouldn't have included MEM_OE condition in the always block. That should only appear with the assign statement. That's kind of a standard way of manipulating this bi-directional port stuff. In this case, the MEM_RW actually represents the select signal for tri-state buffer in the bi-directional port.

assign MEM_DATA=(MEM_OE&&!MEM_RW)?data_out:18'bz;
always@(posedge clk)
begin
  if(!MEM_RW&&MEM_OE)
    data_out<=Memory;  
  else if(MEM_RW&&MEM_OE)
    begin
      Memory<=MEM_DATA;
     
    end

end