How to write a verilog memory code with a inout data port

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But anyway I didn't get one clock read operation.

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I don't exactly understand what's going on in your simulation. A RAM with unregistered outputs will send the data after latching the read address, without an additional cycle of delay. You can check in the respective device handbooks. Also your Verilog code is specifying this operation. So the design compiler should either implement or reject it, but not add a delay cycle. Did you perform a functional or timing simulation? What's the involved device, what's the clock frequency?