How to write a verilog memory code with a inout data port

my current src:

module mem_test(address, MEM_RW, MEM_OE, MEM_DATA_bidir, clk);

input [7:0] address;

input MEM_RW, MEM_OE;

//mem_oe=1 for memory output enable, mem_oe=0 output=zzzz...

//mem_rw=0 for read, mem_rw=1 for write

inout [17:0] MEM_DATA_bidir;

input clk;

reg [17:0] data_out;

wire [17:0] MEM_DATA;

reg [17:0] Memory [0:255];

wire Read = MEM_OE && (!MEM_RW) ;

wire Write = MEM_OE && MEM_RW ;

assign MEM_DATA_bidir = Read ? data_out : 'z ;

always@(posedge clk) begin

if (Write) Memory[address] <= MEM_DATA_bidir ;

data_out <= Memory[address] ;

end

endmodule