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bark,
Oh so the read operation has to take two cycles if i want to use memory...
Then how should i modify my verilog code?
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No, the read does not take 2 cycles unless there are registers on memory out or in. In fact there is a way to write and read in the same cycle. You should use the MegaWizard to create the kind of memory that you want. Click on the "Documentation" button to get sample waveforms after you have set the options.
Also the memory does not have tri-state drivers but you can hang any driver type on the memory output then have total control of the gating,
The memory latches the inputs at clock time, but if you also register the input there will be a cycle delay.
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