How to synthesize a CPU with a FSM behavioral module

Hi all,

I'm new in Verilog and FPGA design.

I write a code to implement simple ALU and Memories to do simple STORE and ADD operation.

After compilation, the tool reports that Clock Hold not operational because

the clock Skew>Data Delay. And there are also some warnings that latches are inferred.

I am wondering is there something wrong with my code? For my CPU, there is only one general purpose register AC(accumulator). MA is the address register and MD is the data register. IA, IB are index registers, which are not used in this case.

In the state3 of my FSM,if it's indirect addressing mode, I think I am trying to write values to AC, MA and MD twice in one clock cycle. Will that cause problems?

If anyone can help, thanks a lot...

module CPU1(clk,reset,AC);
input clk,reset; 
output  AC;
reg  MEM;
reg CF;
reg  PC,MA,IA,IB;
reg  MD,AC,IR;
reg  state,nextstate;
parameter state0=2'b00,
          state1=2'b01,
          state2=2'b10,
          state3=2'b11,
          
          DIRECT=2'b00,
          INDIRECT=2'b01,
          INDEXED=2'b10,
          OTHER=2'b11,
          
          LOAD=3'b000,
          ADD=3'b001;
          
initial
begin
PC=0;
IR=0;
MEM=000_00_0000000000100; //Load M into AC
MEM=001_00_0000000000011; //Add M to AC
MEM=000_00_0000000000000; //DOES NOTHING
MEM=000000000000001100; //DATA
MEM=000000000000000010; //DATA
end
always@(*)
case(state)
state0:begin
         nextstate=state1;
         MA=PC;
         PC=PC+1;
       end
       
state1:begin
         nextstate=state2;
         MD=MEM;
       end
       
state2:begin
         nextstate=state3;
         IR=MD;
       end
state3:begin
         case(IR)
         LOAD:begin
                case(IR)
                DIRECT:begin 
                         MA=IR;
                         MD=MEM;
                         AC=MD;
                       end
                INDIRECT:begin
                           MA=IR;
                           MD=MEM;
                           AC=MD;
                           MA=AC;
                           MD=MEM;
                           AC=MD;
                         end
                INDEXED:;
                OTHER:;
                endcase
              end
                          
         ADD:begin
               case(IR)
               DIRECT:begin
                        MA=IR;
                        MD=MEM;
                        AC=AC+MD;
                      end
               INDIRECT:begin
                          MA=IR;
                          MD=MEM;
                          MA=MD;
                          MD=MEM;
                          AC=AC+MD;
                        end
               INDEXED:;
               OTHER:;
               endcase
             end
        
         default:begin
                   case(IR)
                   DIRECT:begin
                        MA=IR;
                        MD=MEM;
                        AC=AC+MD;
                      end
                   INDIRECT:begin
                          MA=IR;
                          MD=MEM;
                          MA=MD;
                          MD=MEM;
                          AC=AC+MD;
                        end
                   INDEXED:;
                   OTHER:;
                   endcase
                 end
         
         
         endcase
       end
       
default:begin
          nextstate<=state0;
        end
endcase
always@(posedge clk)
if(~reset)
state<=state0;
else
state<=nextstate;
endmodule