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Altera_Forum
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15 years ago

How to synthesize a CPU with a FSM behavioral module

Hi all, I'm new in Verilog and FPGA design. I write a code to implement simple ALU and Memories to do simple STORE and ADD operation. After compilation, the tool reports that Clock Hold ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

kaz,

I added the accumulator as the output. But I met another problem.

I could not find the values of M in simulation.

Are we able to download data to Memory on FPGA with verilog inital block as I did in this case?