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Altera_Forum
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15 years ago

How to synthesize a CPU with a FSM behavioral module

Hi all, I'm new in Verilog and FPGA design. I write a code to implement simple ALU and Memories to do simple STORE and ADD operation. After compilation, the tool reports that Clock Hold ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

What do you do to these M values? do they affect the output?

Compilers are designed (by software people) to remove any logic that does not affect the outputs because it is seen as useless waste of logic and will affect the reputation of their devices so be kind to them.