Honored Contributor
Honored Contributorclock skew is a repeated scenario for many beginners and has been addressed in several threads.
In FPGAs (as opposed to ASICs) the designer must use the clock network (dedicated clock pins and routing). As such the fitter takes care of tSU of all internal registers by restricting fmax and takes care of tH by making sure that clock arrives at latching register not delayed with respect to data. If the designer opted for gating the clock then clock may be delayed more than data and the fitter cries in despair. So if you have to gate the clock make sure you put it back to rest on global routing. I don't normally gate my clocks at all. If I have to then I use altera's clock mux to bridge over. You can also use settings in quartus or HDL attributes to reconnect.
