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Altera_Forum
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15 years ago

How to synthesize a CPU with a FSM behavioral module

Hi all, I'm new in Verilog and FPGA design. I write a code to implement simple ALU and Memories to do simple STORE and ADD operation. After compilation, the tool reports that Clock Hold ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Do you have outputs?

As far as I know every digital module (in fact any system) is based on having inputs and outputs. The functionality decides outputs based on inputs and internal states. I know some may not have explicit input e.g. oscillators but still have input...

edit: only exception is testbench (simulator tools)