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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to specify timing constraints between 2 memory ports

I have a design with 2 memory read ports (M1 and M2) connected as follows

M1 ---> combinational-gates----> M2

i.e. M1's data out feeds the address of M2.

M1 and M2 are clocked by the outputs of a counter so I know exactly how much

delay is allowed between the data launch at M1 and capture at M2.

I don't know how to constrain this in SDC.

Can I do this:

1. call M1 and M2's clocks as exclusive or unrelated

2. set_max_delay -from M1's data-out -to M2's inputs <my-known-value>

Will quartus report if it cannot place the gates to honor my constraint?

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The "more correct" way would be to put generated clock assignments(where the -source is whatever drives the counter's clock) on the counter bit that creates the clock. That way skew will be accounted for back to the clock source.

    If you make the exclusive/unrelated, there is no way to re-relate them, as false paths, clock groups always have priority.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Rsyc,

    many thanks. I considered that idea, but here is the problem.

    suppose m1 is clocked by step 5 of the counter and m2 is clocked by step 8 of

    the counter. Then I know I have 3 clock cycles between m1 and m2.

    If I do a generated clock, then how would quartus know about this.

    Would it not infer that the m1->m2 path is very short (due to being generated

    by same clock) and hence fail constraint?

    thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The generated clocks will have a slower period when you create them. For example, if you had a 10ns clock as your base clock, then one generated clock might have a "-divide_by 32" option set, making it a 320ns period, and another with a "-divide by 128", making it 1,280ns. The setup relationship between those clocks would now be 320ns. If you don't like that, multicycles can change it.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    My interpretation of post# 3 is that M1 and M2 have the same frequency but they're phase shifted.

    So, "-divide_by X -phase Y" for M1 and "-divide_by X -phase Z" for M2.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    hi:

    I have a follow up question: Will the generated clock trick in SDC work

    for clock enables as well? If I move the logic to enables such that the 2 state

    devices have the same clock but 2 derived clock enables, How can I specify

    this in SDC?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Use multi-cycle exceptions for that.

    You need to figure out how many clock cycles the path has to propagate a change.

    Ie, if M1 is enabled at clock 5 and M2 is enabled at clock 8, then a change is always launched by M1 3 cycles before M2 captures it.

    That's your setup multiplier: 3.

    Your hold multiplier is always N-1 (for enabled related multi-cycles). In this case, 2.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Use get_fanouts. There should be a number of posts in this forum, but something like:

    set fouts [get_fanouts {enable_register_name}]

    set_multicycle_path -setup 2 -from $fouts -to $fouts

    set_multicycle_path -hold 1 -from $fouts -to $fouts

    If it's a divide-by-2 register(i.e. it feeds back on itself), you might need to remove it from the group using remove_from_collection. Also, many designs don't use the -from, just the -to, since all paths to these registers are multicycles.