How to specify timing constraints between 2 memory ports

The generated clocks will have a slower period when you create them. For example, if you had a 10ns clock as your base clock, then one generated clock might have a "-divide_by 32" option set, making it a 320ns period, and another with a "-divide by 128", making it 1,280ns. The setup relationship between those clocks would now be 320ns. If you don't like that, multicycles can change it.