How to specify timing constraints between 2 memory ports

Hi Rsyc,

many thanks. I considered that idea, but here is the problem.

suppose m1 is clocked by step 5 of the counter and m2 is clocked by step 8 of

the counter. Then I know I have 3 clock cycles between m1 and m2.

If I do a generated clock, then how would quartus know about this.

Would it not infer that the m1->m2 path is very short (due to being generated

by same clock) and hence fail constraint?

thanks.