How to specify timing constraints between 2 memory ports

Use multi-cycle exceptions for that.

You need to figure out how many clock cycles the path has to propagate a change.

Ie, if M1 is enabled at clock 5 and M2 is enabled at clock 8, then a change is always launched by M1 3 cycles before M2 captures it.

That's your setup multiplier: 3.

Your hold multiplier is always N-1 (for enabled related multi-cycles). In this case, 2.