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Altera_Forum
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13 years ago

How to specify timing constraints between 2 memory ports

I have a design with 2 memory read ports (M1 and M2) connected as follows M1 ---> combinational-gates----> M2 i.e. M1's data out feeds the address of M2. M1 and M2 are clocked by the ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

The "more correct" way would be to put generated clock assignments(where the -source is whatever drives the counter's clock) on the counter bit that creates the clock. That way skew will be accounted for back to the clock source.

If you make the exclusive/unrelated, there is no way to re-relate them, as false paths, clock groups always have priority.